ibex

Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.

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Ibex RISC-V Core

Ibex is a small and efficient, 32-bit, in-order RISC-V core with a 2-stage pipeline that implements
the RV32IMC instruction set architecture.

Ibex offers several configuration parameters to meet the needs of various application scenarios.
The options include two different choices for the architecture of the multiplier and divider unit,
as well as the possibility to drop the support for the "M" extension completely. In addition, the
"E" extension can be enabled when opting for a minimum-area configuration.

This core was initially developed as part of the PULP platform
under the name "Zero-riscy" [1], and has been
contributed to lowRISC who maintains it and develops it further. It is
under active development, with further code cleanups, feature additions, and test and verification
planned for the future.

Documentation

The Ibex user manual can be
read online at ReadTheDocs. It is also contained in
the doc folder of this repository.

Contributing

We highly appreciate community contributions. To ease our work of reviewing your contributions,
please:

  • Create your own branch to commit your changes and then open a Pull Request.
  • Split large contributions into smaller commits addressing individual changes or bug fixes. Do not
    mix unrelated changes into the same commit!
  • Write meaningful commit messages. For more information, please check out the contribution
    guide
    .
  • If asked to modify your changes, do fixup your commits and rebase your branch to maintain a
    clean history.

When contributing SystemVerilog source code, please try to be consistent and adhere to our Verilog
coding style guide
.

When contributing C or C++ source code, please try to adhere to the OpenTitan C++ coding style
guide
.
All C and C++ code should be formatted with clang-format before committing.
Either run clang-format -i filename.cc or git clang-format on added files.

To get started, please check out the "Good First Issue"
list
.

Issues and Troubleshooting

If you find any problems or issues with Ibex or the documentation, please check out the issue
tracker
and create a new issue if your problem is
not yet tracked.

Questions?

Do not hesitate to contact us, e.g., on our public Ibex channel on
Zulip
!

License

Unless otherwise noted, everything in this repository is covered by the Apache
License, Version 2.0 (see LICENSE for full text).

Credits

Many people have contributed to Ibex through the years. Please have a look at
the credits file and the commit history for more information.

References

  1. Schiavone, Pasquale Davide, et al. "Slow and steady wins the race? A comparison of
    ultra-low-power RISC-V cores for Internet-of-Things applications."
    27th International Symposium on Power and Timing Modeling, Optimization and Simulation
    (PATMOS 2017)

主要指標

概覽
名稱與所有者lowRISC/ibex
主編程語言SystemVerilog
編程語言SystemVerilog (語言數: 14)
平台
許可證Apache License 2.0
所有者活动
創建於2017-08-08 12:16:36
推送於2025-04-25 13:47:34
最后一次提交2025-04-22 19:44:49
發布數8
最新版本名稱pulpissimo-v6.1.1 (發布於 )
第一版名稱pulpino-v1.0.0 (發布於 )
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