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vtr-verilog-to-routing

Verilog to Routing -- 用于 FPGA 研究的开源 CAD 流程。「Verilog to Routing -- Open Source CAD Flow for FPGA Research」

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Verilog to Routing (VTR)

介绍

Verilog-to-Routing（VTR）项目是一项全球性的合作，旨在为进行 FPGA 体系结构和 CAD 研究与开发提供开源框架。 VTR 设计流程将数字电路的 Verilog 描述和目标 FPGA 架构的描述作为输入。 然后执行：

  • 精细化与综合（ODIN II）
  • 逻辑优化与技术映射（ABC）
  • 包装、放置、路由和时序分析（VPR）

生成 FPGA 速度和面积的结果。VTR 包括一套已知的基准设计与设计流程。

VTR 还可以生产 FASM 来对某些商用 FPGA 进行编程（通过 Symbiflow）

文档

VTR 的完整文档包括教程、VTR 设计流程的描述以及工具选项。

另请查看我们的其他支持资源。

许可

通常，大多数代码均获得 MIT 许可，但 ABC 除外，它是根据其自己的（许可）条款分发的。 有关详细信息，请参见完整许可证。

如何引用

以下论文可用作 VTR 的一般引文：

K. E. Murray, O. Petelin, S. Zhong, J. M. Wang, M. ElDafrawy, J.-P. Legault, E. Sha, A. G. Graham, J. Wu, M. J. P. Walker, H. Zeng, P. Patros, J. Luu, K. B. Kent and V. Betz "VTR 8: High Performance CAD and Customizable FPGA Architecture Modelling", ACM TRETS, 2020.

Bibtex: 

@article{vtr8,
  title={VTR 8: High Performance CAD and Customizable FPGA Architecture Modelling},
  author={Murray, Kevin E. and Petelin, Oleg and Zhong, Sheng and Wang, Jai Min and ElDafrawy, Mohamed and Legault, Jean-Philippe and Sha, Eugene and Graham, Aaron G. and Wu, Jean and Walker, Matthew J. P. and Zeng, Hanqing and Patros, Panagiotis and Luu, Jason and Kent, Kenneth B. and Betz, Vaughn},
  journal={ACM Trans. Reconfigurable Technol. Syst.},
  year={2020}
}

下载

对于大多数 VTR 用户（而不是活跃的开发人员），您应该下载经过全面回归测试的最新官方 VTR 版本。

构建

在类似 Unix 的系统上，从 VTR 根目录运行 make。

有关更多详细信息，请参见构建说明。

Docker

我们提供了一个 Dockerfile，该文件设置了运行 VTR 所需的所有必要软件包。有关更多详细信息，请参见此处。

邮件列表

如果您有任何疑问，或者想了解最新的VTR，请考虑加入我们的邮件列表：

VTR-Announce：VTR 发布公告（访问量低）
VTR-Users：有关使用 VTR 的讨论
VTR-Devel：有关 VTR 开发的讨论
VTR-Commits：VTR 修订控制提交

开发

这是 Verilog-to-Routing 项目的开发干线。与我们创建的打包好的版本不同，您正在使用处于不断变化的状态的代码。您应该期望这些工具并不总是稳定的，并且需要更多的工作来使流程运行。

对于新开发人员，请执行本教程。一旦您加速，您将被引导回到此处。

VTR开发遵循经典的集中式存储库（类似svn）的工作流程。 “master”分支应该是该项目的最新稳定版本。开发人员在开发开始时签出代码的本地副本，然后进行定期更新（例如 git pull --rebase）以与 GitHub master 保持同步。当开发人员将经过测试的工作变更放回 master 时，他/她将执行 git push 操作。不稳定的代码应保留在开发人员的本地副本中。

我们使用 BuildBot 对中继进行自动化测试，以验证功能和结果质量（QoR）。

重要说明：损坏的构建必须首先得到解决。如果您的提交破坏了任何自动回归测试，则将破坏构建。

有关更多信息，请参见开发人员自述文件。

为 VTR 做贡献

如果您想为VTR做出贡献，请参阅我们的贡献准则。

（The first version translated by vz on 2020.07.18）

主要指标

概览
名称与所有者verilog-to-routing/vtr-verilog-to-routing
主编程语言C++
编程语言Makefile (语言数: 22)
平台Docker, Linux, Unix-like
许可证Other
所有者活动
创建于2015-06-26 15:24:42
推送于2025-04-24 21:45:39
最后一次提交2025-04-24 09:36:25
发布数14
最新版本名称v9.0.0 (发布于 )
第一版名称vtr_v7+ (发布于 2014-05-04 01:12:44)
用户参与
星数1.1k
关注者数64
派生数408
提交数22.2k
已启用问题?
问题数1068
打开的问题数447
拉请求数1573
打开的拉请求数54
关闭的拉请求数297
项目设置
已启用Wiki?
已存档?
是复刻?
已锁定?
是镜像?
是私有?

Verilog to Routing (VTR)

Build Status Documentation Status

Introduction

The Verilog-to-Routing (VTR) project is a world-wide collaborative effort to provide a open-source framework for conducting FPGA architecture and CAD research and development.
The VTR design flow takes as input a Verilog description of a digital circuit, and a description of the target FPGA architecture.
It then performs:

  • Elaboration & Synthesis (ODIN II)
  • Logic Optimization & Technology Mapping (ABC)
  • Packing, Placement, Routing & Timing Analysis (VPR)

to generate FPGA speed and area results.
VTR also includes a set of benchmark designs known to work with the design flow.

Documentation

VTR's full documentation includes tutorials, descriptions of the VTR design flow, and tool options.

Also check out our additional support resources.

License

Generally most code is under MIT license, with the exception of ABC which is distributed under its own (permissive) terms.
See the full license for details.

How to Cite

The following paper may be used as a general citation for VTR:

J. Luu, J. Goeders, M. Wainberg, A. Somerville, T. Yu, K. Nasartschuk, M. Nasr, S. Wang, T. Liu, N. Ahmed, K. B. Kent, J. Anderson, J. Rose and V. Betz "VTR 7.0: Next Generation Architecture and CAD System for FPGAs," ACM TRETS, Vol. 7, No. 2, June 2014, pp. 6:1 - 6:30.

Bibtex:

@article{vtr2014,
  title={{VTR 7.0: Next Generation Architecture and CAD System for FPGAs}},
  author={Luu, Jason and Goeders, Jeff and Wainberg, Michael and Somerville, Andrew and Yu, Thien and Nasartschuk, Konstantin and Nasr, Miad and Wang, Sen and Liu, Tim and Ahmed, Norrudin and Kent, Kenneth B. and Anderson, Jason and Rose, Jonathan and Betz, Vaughn},
  journal = {ACM Trans. Reconfigurable Technol. Syst.},
  month={June},
  volume={7},
  number={2},
  pages={6:1--6:30},
  year={2014}
}

Download

For most users of VTR (rather than active developers) you should download the latest official VTR release, which has been fully regression tested.

Building

On unix-like systems run make from the root VTR directory.

For more details see the building instructions.

Docker

We provide a Dockerfile that sets up all the necessary packages for VTR to run.
For more details see here.

Mailing Lists

If you have questions, or want to keep up-to-date with VTR, consider joining our mailing lists:

VTR-Announce: VTR release announcements (low traffic)

VTR-Users: Discussions about using VTR

VTR-Devel: Discussions about VTR development

VTR-Commits: VTR revision control commits

Development

This is the development trunk for the Verilog-to-Routing project.
Unlike the nicely packaged releases that we create, you are working with code in a constant state of flux.
You should expect that the tools are not always stable and that more work is needed to get the flow to run.

For new developers, please do the tutorial.
You will be directed back here once you ramp up.

VTR development follows a classic centralized repository (svn-like) workflow.
The 'master' branch is supposed to be the most current stable version of the project.
Developers checkout a local copy of the code at the start of development, then do regular updates (e.g. git pull --rebase) to keep in sync with the GitHub master.
When a developer has a tested, working change to put back into the trunk, he/she performs a git push operation.
Unstable code should remain in the developer's local copy.

We do automated testing of the trunk using BuildBot to verify functionality and Quality of Results (QoR).

IMPORTANT: A broken build must be fixed at top priority. You break the build if your commit breaks any of the automated regression tests.

For additional information see the developer README.

Contributing to VTR

If you'd like to contribute to VTR see our Contribution Guidelines.

Contributors

Please keep this up-to-date

Professors: Kenneth Kent, Vaughn Betz, Jonathan Rose, Jason Anderson, Peter Jamieson

Research Assistants: Aaron Graham

Graduate Students: Kevin Murray, Jason Luu, Oleg Petelin, Mohamed Eldafrawy, Jeffrey Goeders, Chi Wai Yu, Andrew Somerville, Ian Kuon, Alexander Marquardt, Andy Ye, Wei Mark Fang, Tim Liu, Charles Chiasson, Panagiotis (Panos) Patros, Jean-Philippe Legault, Aaron Graham, Nasrin Eshraghi Ivari, Maria Patrou, Scott Young

Summer Students: Opal Densmore, Ted Campbell, Cong Wang, Peter Milankov, Scott Whitty, Michael Wainberg, Suya Liu, Miad Nasr, Nooruddin Ahmed, Thien Yu, Long Yu Wang, Matthew J.P. Walker, Amer Hesson, Sheng Zhong, Hanqing Zeng, Vidya Sankaranarayanan, Jia Min Wang, Eugene Sha, Jean-Philippe Legault, Richard Ren, Dingyu Yang, Alexandrea Demmings, Hillary Soontiens, Julie Brown

Companies: Intel, Huawei, Lattice, Altera Corporation, Texas Instruments, Google

Funding Agencies: NSERC, Semiconductor Research Corporation