Verilog to Routing (VTR)
Verilog to Routing -- 用于 FPGA 研究的开源 CAD 流程。「Verilog to Routing -- Open Source CAD Flow for FPGA Research」
Main metrics
Overview
| Name With Owner | verilog-to-routing/vtr-verilog-to-routing |
|---|---|
| Primary Language | C++ |
| Program language | Makefile (Language Count: 18) |
| Platform | Docker, Linux, Unix-like |
| License: | Other |
| Release Count | 14 |
| Last Release Name | v9.0.0 (Posted on ) |
| First Release Name | vtr_v7+ (Posted on 2014-05-04 01:12:44) |
| Created At | 2015-06-26 15:24:42 |
| Pushed At | 2025-07-25 00:15:41 |
| Last Commit At | 2025-07-24 18:25:13 |
| Stargazers Count | 1123 |
| Watchers Count | 66 |
| Fork Count | 422 |
| Commits Count | 23183 |
| Has Issues Enabled | |
| Issues Count | 1109 |
| Issue Open Count | 113 |
| Pull Requests Count | 1728 |
| Pull Requests Open Count | 54 |
| Pull Requests Close Count | 312 |
| Has Wiki Enabled | |
| Is Archived | |
| Is Fork | |
| Is Locked | |
| Is Mirror | |
| Is Private |
