ibex
Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.
Main metrics
Overview
| Name With Owner | lowRISC/ibex |
|---|---|
| Primary Language | SystemVerilog |
| Program language | SystemVerilog (Language Count: 14) |
| Platform | |
| License: | Apache License 2.0 |
| Release Count | 8 |
| Last Release Name | pulpissimo-v6.1.1 (Posted on ) |
| First Release Name | pulpino-v1.0.0 (Posted on ) |
| Created At | 2017-08-08 12:16:36 |
| Pushed At | 2025-04-25 13:47:34 |
| Last Commit At | 2025-04-22 19:44:49 |
| Stargazers Count | 1521 |
| Watchers Count | 99 |
| Fork Count | 599 |
| Commits Count | 2805 |
| Has Issues Enabled | |
| Issues Count | 856 |
| Issue Open Count | 193 |
| Pull Requests Count | 1290 |
| Pull Requests Open Count | 27 |
| Pull Requests Close Count | 94 |
| Has Wiki Enabled | |
| Is Archived | |
| Is Fork | |
| Is Locked | |
| Is Mirror | |
| Is Private |
