ibex
Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.
Main metrics
Overview
| Name With Owner | lowRISC/ibex |
|---|---|
| Primary Language | SystemVerilog |
| Program language | SystemVerilog (Language Count: 16) |
| Platform | |
| License: | Apache License 2.0 |
| Release Count | 8 |
| Last Release Name | pulpissimo-v6.1.1 (Posted on ) |
| First Release Name | pulpino-v1.0.0 (Posted on ) |
| Created At | 2017-08-08 12:16:36 |
| Pushed At | 2025-06-10 05:37:39 |
| Last Commit At | 2025-06-09 11:29:20 |
| Stargazers Count | 1567 |
| Watchers Count | 102 |
| Fork Count | 614 |
| Commits Count | 2825 |
| Has Issues Enabled | |
| Issues Count | 858 |
| Issue Open Count | 194 |
| Pull Requests Count | 1299 |
| Pull Requests Open Count | 30 |
| Pull Requests Close Count | 95 |
| Has Wiki Enabled | |
| Is Archived | |
| Is Fork | |
| Is Locked | |
| Is Mirror | |
| Is Private |
