ibex
Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.
Main metrics
Overview
| Name With Owner | lowRISC/ibex |
|---|---|
| Primary Language | SystemVerilog |
| Program language | SystemVerilog (Language Count: 18) |
| Platform | |
| License: | Apache License 2.0 |
| Release Count | 8 |
| Last Release Name | pulpissimo-v6.1.1 (Posted on ) |
| First Release Name | pulpino-v1.0.0 (Posted on ) |
| Created At | 2017-08-08 12:16:36 |
| Pushed At | 2025-09-19 16:24:37 |
| Last Commit At | 2025-08-21 10:25:01 |
| Stargazers Count | 1631 |
| Watchers Count | 104 |
| Fork Count | 648 |
| Commits Count | 2859 |
| Has Issues Enabled | |
| Issues Count | 875 |
| Issue Open Count | 205 |
| Pull Requests Count | 1312 |
| Pull Requests Open Count | 33 |
| Pull Requests Close Count | 100 |
| Has Wiki Enabled | |
| Is Archived | |
| Is Fork | |
| Is Locked | |
| Is Mirror | |
| Is Private |
