ibex
Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.
Main metrics
Overview
| Name With Owner | lowRISC/ibex |
|---|---|
| Primary Language | SystemVerilog |
| Program language | SystemVerilog (Language Count: 17) |
| Platform | |
| License: | Apache License 2.0 |
| Release Count | 8 |
| Last Release Name | pulpissimo-v6.1.1 (Posted on ) |
| First Release Name | pulpino-v1.0.0 (Posted on ) |
| Created At | 2017-08-08 12:16:36 |
| Pushed At | 2025-07-28 15:48:39 |
| Last Commit At | 2025-07-28 14:17:56 |
| Stargazers Count | 1595 |
| Watchers Count | 103 |
| Fork Count | 638 |
| Commits Count | 2851 |
| Has Issues Enabled | |
| Issues Count | 863 |
| Issue Open Count | 197 |
| Pull Requests Count | 1308 |
| Pull Requests Open Count | 31 |
| Pull Requests Close Count | 98 |
| Has Wiki Enabled | |
| Is Archived | |
| Is Fork | |
| Is Locked | |
| Is Mirror | |
| Is Private |
